﻿using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using Super64.Emulation;

namespace Super64.Emulation
{
    public class M6510
    {
        public ushort pc;
        public byte s;
        public Memory mem;

        private bool CF;
        private bool ZF;
        private bool IF;
        private bool DF;
        private bool OF;
        private bool SF;

        public ushort sp
        {
            get
            {
                return (ushort)(0x100 + s);
            }
            set
            {
                s = (byte)(value & 0xFF);
            }
        }
        public byte flags
        {
            get
            {
                byte res = 0x20;
                if (CF) res |= 1;
                if (ZF) res |= 2;
                if (IF) res |= 4;
                if (DF) res |= 8;
                if (OF) res |= 64;
                if (SF) res |= 128;
                return res;
            }
            set
            {
                if ((value & 1) == 1) CF = true;
                else CF = false;
                if ((value & 2) == 2) ZF = true;
                else ZF = false;
                if ((value & 4) == 4) IF = true;
                else IF = false;
                if ((value & 8) == 8) DF = true;
                else DF = false;
                if ((value & 64) == 64) OF = true;
                else OF = false;
                if ((value & 128) == 128) SF = true;
                else SF = false;
            }
        }

        public byte a;
        public byte x;
        public byte y;

        private byte tmp1;
        private byte tmp2;
        private ushort tmp3;
        private ushort tmp4;

        public bool reset;
        public byte instructionreg;
        public byte cycle;

        public M6510()
        {
            reset = true;
            cycle = 0;
            mem = new Memory();
        }

        public void tick()
        {
            if (reset)
            {
                switch (cycle)
                {
                    case 0:
                        {
                            s = 0;
                            pc = 0xFF;
                            instructionreg = 0;
                            mem.rb(pc);
                            cycle++;
                            break;
                        }
                    case 1:
                        {
                            mem.rb(pc);
                            cycle++;
                            break;
                        }
                    case 2:
                        {
                            mem.rb(pc);
                            cycle++;
                            break;
                        }
                    case 3:
                        {
                            mem.rb(sp);
                            s--;
                            cycle++;
                            break;
                        }
                    case 4:
                        {
                            mem.rb(sp);
                            s--;
                            cycle++;
                            break;
                        }
                    case 5:
                        {
                            mem.rb(sp);
                            s--;
                            cycle++;
                            break;
                        }
                    case 6:
                        {
                            pc = (ushort)((pc & 0xFF00) | mem.rb(0xFFFC));
                            cycle++;
                            break;
                        }
                    case 7:
                        {
                            pc = (ushort)((pc & 0xFF) | (mem.rb(0xFFFD) << 8));
                            cycle++;
                            break;
                        }
                    case 8:
                        {
                            instructionreg = mem.rb(pc);
                            pc++;
                            reset = false;
                            cycle = 0;
                            break;
                        }
                }
            }
            else
            {
                Console.WriteLine((uint)instructionreg);
                Console.WriteLine((uint)pc);
                switch (instructionreg)
                {
                    case 0x00:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.wb(sp, (byte)(pc >> 8));
                                        s--;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.wb(sp, (byte)(pc));
                                        s--;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(sp, (byte)(flags | 0x10));
                                        s--;
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        pc = (ushort)((pc & 0xFF00) | mem.rb(0xFFFE));
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        pc = (ushort)((pc & 0xFF) | (mem.rb(0xFFFF) << 8));
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x01:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        a |= (byte)mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x02:
                        {
                            reset = true;
                            cycle = 9;
                            break;
                        }
                    case 0x03:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp3 |= (byte)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if (tmp1 >= 0x80) CF = true;
                                        else CF = false;
                                        tmp1 <<= 1;
                                        a |= tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 6:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x04:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x05:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a |= mem.rb(tmp1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x06:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if (tmp2 >= 0x80) CF = true;
                                        else CF = false;
                                        tmp2 = (byte)(tmp2 << 1);
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x07:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if (tmp2 >= 0x80) CF = true;
                                        else CF = false;
                                        a |= (byte)(tmp2 << 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x08:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.wb(sp, flags);
                                        s--;
                                        instructionreg = mem.rb(pc);
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x09:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a |= tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x0A:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        if (a >= 0x80) CF = true;
                                        else CF = false;
                                        a <<= 1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x0B:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a &= tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a >= 0x80) CF = true;
                                        else CF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x0C:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.rb(tmp3);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x0D:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        a |= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x0E:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if (tmp1 >= 0x80) CF = true;
                                        else CF = false;
                                        tmp1 <<= 1;
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x0F:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if (tmp1 >= 0x80) CF = true;
                                        else CF = false;
                                        a |= (byte)(tmp1 << 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x10:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (!SF)
                                        {
                                            if (tmp1 < 0x80)
                                            {
                                                tmp3 = (ushort)(pc + tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) + tmp1));
                                            }
                                            else
                                            {
                                                tmp1 = (byte)(~tmp1 + 1);
                                                tmp3 = (ushort)(pc - tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) - tmp1));
                                            }
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (tmp3 < pc)
                                        {
                                            pc -= 0x100;
                                            cycle++;
                                        }
                                        else if (tmp3 > pc)
                                        {
                                            pc += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x11:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a |= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 4:
                                    {
                                        a |= (byte)mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x12:
                        {
                            reset = true;
                            cycle = 9;
                            break;
                        }
                    case 0x13:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            if (tmp1 >= 0x80) CF = true;
                                            else CF = false;
                                            a |= (byte)(tmp1 << 1);
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp1 >= 0x80) CF = true;
                                        else CF = false;
                                        a |= (byte)(tmp1 << 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x14:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.rb(tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x15:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        a |= mem.rb(tmp1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x16:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        tmp2 = (byte)(tmp1 << 1);
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (tmp1 >= 0x80) CF = true;
                                        else CF = false;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x17:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if (tmp2 >= 0x80) CF = true;
                                        else CF = false;
                                        a |= (byte)(tmp2 << 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x18:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        CF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x19:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a |= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        a |= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x1A:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x1B:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if (tmp1 >= 0x80) CF = true;
                                        else CF = false;
                                        a |= (byte)(tmp1 << 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x1C:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x1D:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a |= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        a |= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x1E:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        tmp1 <<= 1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x1F:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if (tmp1 >= 0x80) CF = true;
                                        else CF = false;
                                        a |= (byte)(tmp1 << 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x20:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(sp);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(sp, (byte)(pc >> 8));
                                        s--;
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(sp, (byte)(pc & 0xFF));
                                        s--;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc = tmp3;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x21:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        a &= (byte)mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x22:
                        {
                            reset = true;
                            cycle = 9;
                            break;
                        }
                    case 0x23:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp3 |= (byte)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        tmp2 = (byte)((tmp1 << 1) | (byte)(CF ? 1 : 0));
                                        a &= tmp2;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        if (tmp1 >= 0x80) CF = true;
                                        else CF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x24:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = (byte)(a & mem.rb(tmp1));
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if ((tmp2 & 0x40) == 0x40) OF = true;
                                        else OF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x25:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a &= mem.rb(tmp1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x26:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if (tmp2 >= 0x80) CF = true;
                                        else CF = false;
                                        tmp2 = (byte)((tmp2 << 1) | (byte)(CF ? 1 : 0));
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x27:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if (tmp2 >= 0x80) CF = true;
                                        else CF = false;
                                        tmp2 = (byte)((tmp2 << 1) | (byte)(CF ? 1 : 0));
                                        a &= tmp2;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x28:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        s++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        flags = mem.rb(sp);
                                        instructionreg = mem.rb(pc);
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x29:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a &= tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x2A:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        if (a >= 0x80) CF = true;
                                        else CF = false;
                                        a = (byte)((a << 1) | (byte)(CF ? 1 : 0));
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x2B:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a &= tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a >= 0x80) CF = true;
                                        else CF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x2C:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = (ushort)mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = (byte)(a & mem.rb(tmp3));
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if ((tmp2 & 0x40) == 0x40) OF = true;
                                        else OF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x2D:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = (ushort)mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        a &= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x2E:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        bool newCF;
                                        if (tmp1 >= 0x80) newCF = true;
                                        else newCF = false;
                                        tmp1 = (byte)((tmp1 << 1) | (byte)(CF ? 1 : 0));
                                        CF = newCF;
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x2F:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        bool newCF;
                                        if (tmp1 >= 0x80) newCF = true;
                                        else newCF = false;
                                        tmp1 = (byte)((tmp1 << 1) | (byte)(CF ? 1 : 0));
                                        a &= tmp1;
                                        CF = newCF;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x30:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (SF)
                                        {
                                            if (tmp1 < 0x80)
                                            {
                                                tmp3 = (ushort)(pc + tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) + tmp1));
                                            }
                                            else
                                            {
                                                tmp1 = (byte)(~tmp1 + 1);
                                                tmp3 = (ushort)(pc - tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) - tmp1));
                                            }
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (tmp3 < pc)
                                        {
                                            pc -= 0x100;
                                            cycle++;
                                        }
                                        else if (tmp3 > pc)
                                        {
                                            pc += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x31:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a &= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 4:
                                    {
                                        a &= (byte)mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x32:
                        {
                            reset = true;
                            cycle = 9;
                            break;
                        }
                    case 0x33:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        bool newCF;
                                        if (tmp1 >= 0x80) newCF = true;
                                        else newCF = false;
                                        tmp1 = (byte)((tmp1 << 1) | (byte)(CF ? 1 : 0));
                                        a &= tmp1;
                                        CF = newCF;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 6:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x34:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.rb(tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x35:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        a &= mem.rb(tmp1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x36:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if (tmp2 >= 0x80) CF = true;
                                        else CF = false;
                                        tmp2 = (byte)((tmp2 << 1) | (byte)(CF ? 1 : 0));
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x37:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if (tmp2 >= 0x80) CF = true;
                                        else CF = false;
                                        tmp2 = (byte)((tmp2 << 1) | (byte)(CF ? 1 : 0));
                                        a &= tmp2;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x38:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        CF = true;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x39:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a &= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        a &= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x3A:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x3B:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)(tmp3 + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        bool newCF;
                                        if (tmp1 >= 0x80) newCF = true;
                                        else newCF = false;
                                        tmp1 = (byte)((tmp1 << 1) | (byte)(CF ? 1 : 0));
                                        a &= tmp1;
                                        CF = newCF;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x3C:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x3D:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a &= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        a &= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x3E:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)(tmp3 + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        bool newCF;
                                        if (tmp1 >= 0x80) newCF = true;
                                        else newCF = false;
                                        tmp1 = (byte)((tmp1 << 1) | (byte)(CF ? 1 : 0));
                                        CF = newCF;
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x3F:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)(tmp3 + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        bool newCF;
                                        if (tmp1 >= 0x80) newCF = true;
                                        else newCF = false;
                                        tmp1 = (byte)((tmp1 << 1) | (byte)(CF ? 1 : 0));
                                        a &= tmp1;
                                        CF = newCF;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x40:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        s++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        flags = mem.rb(sp);
                                        s++;
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        pc = mem.rb(sp);
                                        s++;
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        pc |= (ushort)(mem.rb(sp) << 8);
                                        s++;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x41:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        a ^= (byte)mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x42:
                        {
                            reset = true;
                            cycle = 9;
                            break;
                        }
                    case 0x43:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        tmp1 >>= 1;
                                        a ^= (byte)mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 6:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x44:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x45:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a ^= mem.rb(tmp1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x46:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if ((tmp2 & 1) == 1) CF = true;
                                        else CF = false;
                                        tmp2 = (byte)(tmp2 >> 1);
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x47:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        if ((tmp2 & 1) == 1) CF = true;
                                        else CF = false;
                                        tmp2 = (byte)(tmp2 >> 1);
                                        a ^= tmp2;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x48:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.wb(sp, a);
                                        s--;
                                        instructionreg = mem.rb(pc);
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x49:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a ^= tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x4A:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        if ((a & 1) == 1) CF = true;
                                        else CF = false;
                                        a >>= 1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x4B:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        a &= tmp1;
                                        if ((a & 1) == 1) CF = true;
                                        else CF = false;
                                        a >>= 1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x4C:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc = tmp3;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x4D:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        a ^= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x4E:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        tmp1 = (byte)(tmp1 >> 1);
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x4F:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        tmp1 = (byte)(tmp1 >> 1);
                                        a ^= tmp1;
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x50:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (!OF)
                                        {
                                            if (tmp1 < 0x80)
                                            {
                                                tmp3 = (ushort)(pc + tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) + tmp1));
                                            }
                                            else
                                            {
                                                tmp1 = (byte)(~tmp1 + 1);
                                                tmp3 = (ushort)(pc - tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) - tmp1));
                                            }
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (tmp3 < pc)
                                        {
                                            pc -= 0x100;
                                            cycle++;
                                        }
                                        else if (tmp3 > pc)
                                        {
                                            pc += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x51:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a ^= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 4:
                                    {
                                        a ^= (byte)mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x52:
                        {
                            reset = true;
                            cycle = 9;
                            break;
                        }
                    case 0x53:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            if ((tmp1 & 1) == 1) CF = true;
                                            else CF = false;
                                            a ^= (byte)(tmp1 >> 1);
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        a ^= (byte)(tmp1 >> 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x54:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.rb(tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x55:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        a ^= mem.rb(tmp1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x56:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 += x;
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        tmp1 = (byte)(tmp1 >> 1);
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x57:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 += x;
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        tmp1 = (byte)(tmp1 >> 1);
                                        a ^= tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x58:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        IF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x59:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a ^= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        a ^= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x5A:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x5B:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        a ^= (byte)(tmp1 >> 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x5C:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x5D:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a ^= tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        a ^= mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x5E:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        tmp1 >>= 1;
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x5F:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        if ((tmp1 & 1) == 1) CF = true;
                                        else CF = false;
                                        a ^= (byte)(tmp1 >> 1);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 5:
                                    {
                                        mem.wb(tmp3, tmp1);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x60:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(sp);
                                        s++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        pc = mem.rb(sp);
                                        s++;
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        pc |= (ushort)(mem.rb(sp) << 8);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        pc++;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x61:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = (byte)(mem.rb(tmp1) + x);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 = (byte)mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        byte res1 = (byte)(a + tmp1 + (CF ? 1 : 0));
                                        uint res2 = (uint)(a + tmp1 + (CF ? 1 : 0));
                                        short res3 = (short)(a + tmp1 + (CF ? 1 : 0));
                                        if (!DF)
                                        {
                                            a += (byte)(tmp1 + (CF ? 1 : 0));
                                        }
                                        else
                                        {
                                            CF = false;
                                            if ((a & 0x0F) > 0x09)
                                            {
                                                a += 0x06;
                                            }
                                            if ((a & 0xF0) > 0x90)
                                            {
                                                a += 0x60;
                                                CF = true;
                                            }
                                        }
                                        if (res1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (res1 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (res2 >= 0 && res2 >= 255) CF = false;
                                        else CF = true;
                                        if (res3 < -128 && res3 > 127) OF = false;
                                        else OF = true;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x62:
                        {
                            reset = true;
                            cycle = 9;
                            break;
                        }
                    case 0x69:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        byte res1 = (byte)(a + tmp1 + (CF ? 1 : 0));
                                        uint res2 = (uint)(a + tmp1 + (CF ? 1 : 0));
                                        short res3 = (short)(a + tmp1 + (CF ? 1 : 0));
                                        if (!DF)
                                        {
                                            a += (byte)(tmp1 + (CF ? 1 : 0));
                                        }
                                        else
                                        {
                                            CF = false;
                                            if ((a & 0x0F) > 0x09)
                                            {
                                                a += 0x06;
                                            }
                                            if ((a & 0xF0) > 0x90)
                                            {
                                                a += 0x60;
                                                CF = true;
                                            }
                                        }
                                        if (res1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (res1 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (res2 >= 0 && res2 >= 255) CF = false;
                                        else CF = true;
                                        if (res3 < -128 && res3 > 127) OF = false;
                                        else OF = true;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x6C:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        pc = (ushort)((pc & 0xFF00) | mem.rb(tmp3));
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | ((tmp3 + 1) & 0xFF));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        pc = (ushort)((pc & 0xFF) | (mem.rb(tmp3) << 8));
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x78:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        IF = true;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x84:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.wb(tmp1, a);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x85:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.wb(tmp1, x);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x86:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.wb(tmp1, x);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x88:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        y--;
                                        if (y >= 0x80) SF = true;
                                        else SF = false;
                                        if (y == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x8A:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        a = x;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x8C:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp3, y);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x8D:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp3, a);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x8E:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp3, x);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x90:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (!CF)
                                        {
                                            if (tmp1 < 0x80)
                                            {
                                                tmp3 = (ushort)(pc + tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) + tmp1));
                                            }
                                            else
                                            {
                                                tmp1 = (byte)(~tmp1 + 1);
                                                tmp3 = (ushort)(pc - tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) - tmp1));
                                            }
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (tmp3 < pc)
                                        {
                                            pc -= 0x100;
                                            cycle++;
                                        }
                                        else if (tmp3 > pc)
                                        {
                                            pc += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x91:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 4:
                                    {
                                        mem.wb(tmp3, a);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x94:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp1, y);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x95:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        mem.rb(tmp1);
                                        tmp1 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp1, a);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x98:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        a = y;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x99:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, a);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x9A:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        s = x;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0x9D:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                        }
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp3, a);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xA0:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        y = tmp1;
                                        if (y >= 0x80) SF = true;
                                        else SF = false;
                                        if (y == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xA2:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        x = tmp1;
                                        if (x >= 0x80) SF = true;
                                        else SF = false;
                                        if (x == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xA4:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        y = tmp1;
                                        if (y >= 0x80) SF = true;
                                        else SF = false;
                                        if (y == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xA8:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        y = a;
                                        if (y >= 0x80) SF = true;
                                        else SF = false;
                                        if (y == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xA9:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        a = tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xAA:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        x = a;
                                        if (x >= 0x80) SF = true;
                                        else SF = false;
                                        if (x == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xAD:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        a = tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xAE:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        x = tmp1;
                                        if (x >= 0x80) SF = true;
                                        else SF = false;
                                        if (x == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xB0:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (CF)
                                        {
                                            if (tmp1 < 0x80)
                                            {
                                                tmp3 = (ushort)(pc + tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) + tmp1));
                                            }
                                            else
                                            {
                                                tmp1 = (byte)(~tmp1 + 1);
                                                tmp3 = (ushort)(pc - tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) - tmp1));
                                            }
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (tmp3 < pc)
                                        {
                                            pc -= 0x100;
                                            cycle++;
                                        }
                                        else if (tmp3 > pc)
                                        {
                                            pc += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xB1:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a = tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 4:
                                    {
                                        a = (byte)mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xB4:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp2 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp2);
                                        y = tmp1;
                                        if (y >= 0x80) SF = true;
                                        else SF = false;
                                        if (y == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xB5:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp2 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 += x;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp2);
                                        a = tmp1;
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xB9:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a = tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        a = mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xBD:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            a = tmp1;
                                            if (a >= 0x80) SF = true;
                                            else SF = false;
                                            if (a == 0x00) ZF = true;
                                            else ZF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        a = mem.rb(tmp3);
                                        if (a >= 0x80) SF = true;
                                        else SF = false;
                                        if (a == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xC8:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        y++;
                                        if (y >= 0x80) SF = true;
                                        else SF = false;
                                        if (y == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xCA:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        x--;
                                        if (x >= 0x80) SF = true;
                                        else SF = false;
                                        if (x == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                   case 0xCD:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        tmp1 = (byte)(a - tmp1);
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (tmp1 < 0x80) CF = true;
                                        else CF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xD0:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (!ZF)
                                        {
                                            if (tmp1 < 0x80)
                                            {
                                                tmp3 = (ushort)(pc + tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) + tmp1));
                                            }
                                            else
                                            {
                                                tmp1 = (byte)(~tmp1 + 1);
                                                tmp3 = (ushort)(pc - tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) - tmp1));
                                            }
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (tmp3 < pc)
                                        {
                                            pc -= 0x100;
                                            cycle++;
                                        }
                                        else if (tmp3 > pc)
                                        {
                                            pc += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xD1:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 = (byte)(mem.rb(tmp1));
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp3 |= (ushort)(mem.rb((ushort)(tmp1 + 1)) << 8);
                                        tmp4 = (ushort)(tmp3 + y);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + y));
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            tmp2 = (byte)(a - tmp1);
                                            if (tmp2 >= 0x80) SF = true;
                                            else SF = false;
                                            if (tmp2 == 0x00) ZF = true;
                                            else ZF = false;
                                            if (tmp2 < 0x80) CF = true;
                                            else CF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 4:
                                    {
                                        tmp2 = (byte)(a - mem.rb(tmp3));
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (tmp2 < 0x80) CF = true;
                                        else CF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xD8:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        DF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xDD:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (byte)(mem.rb(pc) << 8);
                                        tmp4 = (ushort)(tmp3 + x);
                                        tmp3 = (ushort)((tmp3 & 0xFF00) | (byte)((tmp3 & 0xFF) + x));
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = (byte)mem.rb(tmp3);
                                        if (tmp3 != tmp4)
                                        {
                                            tmp3 += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            tmp2 = (byte)(a - tmp1);
                                            if (tmp2 >= 0x80) SF = true;
                                            else SF = false;
                                            if (tmp2 == 0x00) ZF = true;
                                            else ZF = false;
                                            if (tmp2 < 0x80) CF = true;
                                            else CF = false;
                                            instructionreg = mem.rb(pc);
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        tmp2 = (byte)(a - mem.rb(tmp3));
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (tmp2 < 0x80) CF = true;
                                        else CF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xE0:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        tmp2 = (byte)(x - tmp1);
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (tmp2 < 0x80) CF = true;
                                        else CF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xE4:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp1 = mem.rb(tmp1);
                                        pc++;
                                        tmp2 = (byte)(x - tmp1);
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (tmp2 < 0x80) CF = true;
                                        else CF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xE6:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(tmp1);
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        tmp2++;
                                        if (tmp2 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp2 == 0x00) ZF = true;
                                        else ZF = false;
                                        cycle++;
                                        break;
                                    }
                                case 3:
                                    {
                                        mem.wb(tmp1, tmp2);
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xE8:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        mem.rb(pc);
                                        x++;
                                        if (x >= 0x80) SF = true;
                                        else SF = false;
                                        if (x == 0x00) ZF = true;
                                        else ZF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xEC:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp3 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp3 |= (ushort)(mem.rb(pc) << 8);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp1 = mem.rb(tmp3);
                                        tmp1 = (byte)(x - tmp1);
                                        if (tmp1 >= 0x80) SF = true;
                                        else SF = false;
                                        if (tmp1 == 0x00) ZF = true;
                                        else ZF = false;
                                        if (tmp1 < 0x80) CF = true;
                                        else CF = false;
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    case 0xF0:
                        {
                            switch (cycle)
                            {
                                case 0:
                                    {
                                        tmp1 = mem.rb(pc);
                                        pc++;
                                        cycle++;
                                        break;
                                    }
                                case 1:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (ZF)
                                        {
                                            if (tmp1 < 0x80)
                                            {
                                                tmp3 = (ushort)(pc + tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) + tmp1));
                                            }
                                            else
                                            {
                                                tmp1 = (byte)(~tmp1 + 1);
                                                tmp3 = (ushort)(pc - tmp1);
                                                pc = (ushort)((pc & 0xFF00) | (byte)((pc & 0xFF) - tmp1));
                                            }
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 2:
                                    {
                                        tmp2 = mem.rb(pc);
                                        if (tmp3 < pc)
                                        {
                                            pc -= 0x100;
                                            cycle++;
                                        }
                                        else if (tmp3 > pc)
                                        {
                                            pc += 0x100;
                                            cycle++;
                                        }
                                        else
                                        {
                                            instructionreg = tmp2;
                                            pc++;
                                            cycle = 0;
                                        }
                                        break;
                                    }
                                case 3:
                                    {
                                        instructionreg = mem.rb(pc);
                                        pc++;
                                        cycle = 0;
                                        break;
                                    }
                            }
                            break;
                        }
                    default:
                        {
                            instructionreg = mem.rb(pc);
                            pc++;
                            cycle = 0;
                            break;
                        }
                }
            }
        }
    }
}
